/* SPDX-License-Identifier: GPL-2.0 */
/**
 * gmac_const.h - CSP definitions of LomboTech GMAC Driver.
 *
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef __GMAC_CONST_H__
#define __GMAC_CONST_H__

/* Max Channel and Queue Number */
#define LGMAC_CH_MAX		(1)
#define LGMAC_TX_QUEUES_MAX	(1)
#define LGMAC_RX_QUEUES_MAX	(1)

/* FIFO Size */
#define LGMAC_TX_FIFO_SIZE	(4096)
#define LGMAC_RX_FIFO_SIZE	(4096)

/* PHY Interface Type */
#define LGMAC_PHY_TYPE_MII_GMII	(0)		/* MII/GMII */
#define LGMAC_PHY_TYPE_RGMII	(1)		/* RGMII */
#define LGMAC_PHY_TYPE_RMII	(4)		/* RMII */

/* Clock Gate */
#define LGMAC_CLK_GATE_RMII_O	BIT(6)		/* RMII_O */
#define LGMAC_CLK_GATE_TXC_O	BIT(5)		/* TXC_O */
#define LGMAC_CLK_GATE_RMII_I	BIT(4)		/* CLK_RMII_I */
#define LGMAC_CLK_GATE_RX_180_I	BIT(3)		/* CLK_RX_180_I */
#define LGMAC_CLK_GATE_RX_I	BIT(2)		/* CLK_RX_I */
#define LGMAC_CLK_GATE_TX_180_I	BIT(1)		/* CLK_TX_180_I */
#define LGMAC_CLK_GATE_TX_I	BIT(0)		/* CLK_TX_I */

#define LGMAC_CLK_GATE_ALL	(LGMAC_CLK_GATE_RMII_O | \
				 LGMAC_CLK_GATE_TXC_O | \
				 LGMAC_CLK_GATE_RMII_I | \
				 LGMAC_CLK_GATE_RX_180_I | \
				 LGMAC_CLK_GATE_RX_I | \
				 LGMAC_CLK_GATE_TX_180_I | \
				 LGMAC_CLK_GATE_TX_I)

/* GMAC Configuration */
#define LGMAC_CONFIG_ARPEN	BIT(31)		/* ARP Offload Enable */
#define LGMAC_CONFIG_IPC	BIT(27)		/* Checksum Offload */
#define LGMAC_CONFIG_2K		BIT(22)		/* Support for 2K Packets */
#define LGMAC_CONFIG_ACS	BIT(20)		/* Auto Pad or CRC Stripping */
#define LGMAC_CONFIG_WD		BIT(19)		/* Watchdog Disable */
#define LGMAC_CONFIG_PBE	BIT(18)		/* Packet Burst Enable */
#define LGMAC_CONFIG_JD		BIT(17)		/* Jabber Disable */
#define LGMAC_CONFIG_JE		BIT(16)		/* Jumbo Packet Enable */
#define LGMAC_CONFIG_DRO	BIT(10)		/* Disable Receive Own */
#define LGMAC_CONFIG_DCRS	BIT(9)		/* Disable Carrier Sense */
#define LGMAC_CONFIG_DR		BIT(8)		/* Disable Retry */

#define LGMAC_DEF_CONFIG	(LGMAC_CONFIG_JD | LGMAC_CONFIG_PBE | \
				 LGMAC_CONFIG_DCRS)

/* MAC Packet Filter */
#define LGMAC_FILTER_RA		BIT(31)		/* Receive All */
#define LGMAC_FILTER_PM		BIT(4)		/* Pass All Multicast */
#define LGMAC_FILTER_HMC	BIT(2)		/* Hash Multicast */
#define LGMAC_FILTER_PR		BIT(0)		/* Promiscuous Mode */

#define LGMAC_HASH_TABLE_SIZE	(64)

/* Rx Queue Enable */
#define LGMAC_RXQEN_NOT		(0)		/* Not enabled */
#define LGMAC_RXQEN_AV		(1)		/* Enabled for AV */
#define LGMAC_RXQEN_DCB		(2)		/* Enabled for DCB/Generic */

/* Rx Packets Queue Control */
#define LGMAC_ROUTE_MCBCQEN	(5)		/* Multicast and Broadcast */
#define LGMAC_ROUTE_UPQ		(4)		/* Untagged Packet Queue */
#define LGMAC_ROUTE_DCBCPQ	(3)		/* DCB Control Packets Queue */
#define LGMAC_ROUTE_PTPQ	(2)		/* PTP Packets Queue */
#define LGMAC_ROUTE_AVCPQ	(1)		/* AV Untagged Control */

/* CORE Interrupt */
#define LGMAC_INT_LPI		BIT(5)		/* LPI Interrupt */
#define LGMAC_INT_PMT		BIT(4)		/* PMT Interrupt */
#define LGMAC_INT_PHY		BIT(3)		/* PHY Interrupt */
#define LGMAC_INT_RGMII		BIT(0)		/* RGMII Interrupt */

#define LGMAC_DEF_INT_MASK	(0)

/* LPI Control and Status */
#define LGMAC_LPI_TX_EXIT	BIT(1)		/* Transmit LPI Exit */
#define LGMAC_LPI_TX_ENTRY	BIT(0)		/* Transmit LPI Entry */

/* LPI Timer */
#define LGMAC_DEF_LPI_LS_TIMER	(1000)
#define LGMAC_DEF_LPI_TW_TIMER	(30)

/* Tx Scheduling Algorithm */
#define LGMAC_MTL_TSA_WRR	(0)		/* WRR Algorithm */
#define LGMAC_MTL_TSA_WFQ	(1)		/* WFQ Algorithm */
#define LGMAC_MTL_TSA_DWRR	(2)		/* DWRR Algorithm */
#define LGMAC_MTL_TSA_STR	(3)		/* Strict Priority Algorithm */

/* Rx Arbitration Algorithm */
#define LGMAC_MTL_RAA_STR	(0)		/* Strict Priority Algorithm */
#define LGMAC_MTL_RAA_WSP	(1)		/* Weighted Strict Priority */

/* MTL Interrupt Status */
#define LGMAC_MTL_INT_QX(x)	BIT(x)		/* Queue[X] Interrupt Status */

/* Queue Interrupt Control Status */
#define LGMAC_Q_INT_RXOVFIS	BIT(16)		/* Receive Queue Overflow */
#define LGMAC_Q_INT_TXUNFIS	BIT(0)		/* Transmit Queue Underflow */

/* Tx Queue Enable */
#define LGMAC_TXQEN_NOT		(0)		/* Not enabled */
#define LGMAC_TXQEN_AV		(1)		/* Enable in AV mode */
#define LGMAC_TXQEN_ENABLE	(2)		/* Enabled */

/* AXI Burst Length */
#define LGMAC_AXI_BLEN_4	BIT(1)
#define LGMAC_AXI_BLEN_8	BIT(2)
#define LGMAC_AXI_BLEN_16	BIT(3)

/* Rx Watchdog Timer Count */
#define LGMAC_MAX_RX_WDT_CNT	(0xff)
#define LGMAC_MIN_RX_WDT_CNT	(0x20)

/* DMA Channel Interrupt */
#define LGMAC_DMA_CH_INT_NIS	BIT(15)	/* Normal Interrupt Summary */
#define LGMAC_DMA_CH_INT_AIS	BIT(14)	/* Abnormal Interrupt Summary */
#define LGMAC_DMA_CH_INT_CDE	BIT(13)	/* Context Descriptor Error */
#define LGMAC_DMA_CH_INT_FBE	BIT(12)	/* Fatal Bus Error */
#define LGMAC_DMA_CH_INT_ERI	BIT(11)	/* Early Receive Interrupt */
#define LGMAC_DMA_CH_INT_ETI	BIT(10)	/* Early Transmit Interrupt */
#define LGMAC_DMA_CH_INT_RWT	BIT(9)	/* Receive Watchdog Timeout */
#define LGMAC_DMA_CH_INT_RPS	BIT(8)	/* Receive Process Stopped */
#define LGMAC_DMA_CH_INT_RBU	BIT(7)	/* Receive Buffer Unavailable */
#define LGMAC_DMA_CH_INT_RI	BIT(6)	/* Receive Interrupt */
#define LGMAC_DMA_CH_INT_TBU	BIT(2)	/* Transmit Buffer Unavailable */
#define LGMAC_DMA_CH_INT_TPS	BIT(1)	/* Transmit Process Stopped */
#define LGMAC_DMA_CH_INT_TI	BIT(0)	/* Transmit Interrupt */

#define LGMAC_DMA_CH_INT_NOR	(LGMAC_DMA_CH_INT_NIS | LGMAC_DMA_CH_INT_RI | \
				 LGMAC_DMA_CH_INT_TI)
#define LGMAC_DMA_CH_INT_ABNOR	(LGMAC_DMA_CH_INT_AIS | LGMAC_DMA_CH_INT_FBE)
#define LGMAC_DMA_CH_INT_DEF	(LGMAC_DMA_CH_INT_NOR | LGMAC_DMA_CH_INT_ABNOR)
#define LGMAC_DMA_CH_INT_CARE	(LGMAC_DMA_CH_INT_RI | LGMAC_DMA_CH_INT_TI | \
				 LGMAC_DMA_CH_INT_TPS | LGMAC_DMA_CH_INT_FBE)
#define LGMAC_DMA_CH_INT_ALL	(0x3FFFC7)

#endif /* __GMAC_CONST_H__ */
